1. Field of the Invention
The invention relates generally to a memory interface and, more specifically, to a memory controller and a dynamic random access memory (DRAM) interface.
2. Description of the Related Art
Current standard memory interfaces typically implement a parallel command and address bus. For example, the JEDEC specification for DDR3 SDRAM defines sixteen address pins (A0-A15), three bank address pins (BA0-BA2), and five command pins (CS#, CKE#, RAS#, CAS#, WE#), for a total of twenty-four pins. The JEDEC specification for GDDR5 SGRAM defines fourteen address pins (A0-A12, plus RFU (Reserved)) and four bank address pins (BA0-BA3) (sharing nine physical pins via double data rate addressing), an address bus inversion pin (ABI#), and five command pins (CS#, CKE#, RAS#, CAS#, WE#), for a total of fifteen pins.
Other types of interfaces implement a high-speed serial interface. For example, DisplayPort® and Peripheral Component Interconnect Express® (PCIe) have one or more lanes (differential signals for communication) for command and data transfer. However, the serial interfaces typically require extensive calibration in order to provide the necessary bandwidth of data transmission. For example, the PCIe standard defines a link training sequence that must be performed before data may be transmitted over the serial link. The link training sequence discovers the number of lanes in the link, the maximum speed of the link, and the physical properties of the link such as timing skew for each lane. The serial link needs to determine these parameters before the link can be operated at high speeds while maintaining the accuracy of the data transmission. These interfaces may also require a low-speed sideband communication channel to initiate calibration, such as the auxiliary channel in DisplayPort®.
One drawback to conventional memory interfaces is that the parallel command and address bus requires a large number of interconnects. Routing between the memory controller and the memory device may become complex and requires a lot of physical space in the layout of the printed circuit board. Although switching to a purely serial command and address bus may reduce the number of interconnects required, the requirements of extensive calibration causes a latency at power-up before any data may be transmitted over the link. Furthermore, a sideband communication channel may be required in order to calibrate the serial link, which adds extra interconnects that are not used during normal operation.
As the foregoing illustrates, what is needed in the art is an improved technique for sending commands and addresses to a memory device.